A3S Lane
A3S Lane
Priority-based command queue for async task scheduling — Rust, Python, and Node.js
A3S Lane
A3S Lane is a priority-based command queue for async task scheduling. Six built-in lanes with configurable concurrency ensure control commands always preempt LLM generation. Available as a Rust crate, Python package, and Node.js module.
Key Features
- Priority Scheduling — 6 built-in lanes. The highest-priority lane with pending work is always scheduled next.
- Concurrency Control — Per-lane semaphore limits with configurable min/max.
- Retry Policies — Exponential backoff and fixed-delay strategies.
- Dead Letter Queue — Failed commands captured with full context for inspection.
- Persistent Storage — Pluggable storage backend (local filesystem included).
- Event Stream —
EventStreamimplementsfutures_core::Stream; subscribe directly from the manager without threadingEventEmittermanually. - Lane Pressure Events —
queue.lane.pressure/queue.lane.idlewhen queue depth crosses a configured threshold. - Rate Limiting — Token bucket per lane (
distributedfeature). - Priority Boosting — Deadline-based automatic priority escalation (
distributedfeature). - Queue Partitioning — Round-robin and hash-based partitioning for multi-core parallelism.
- Metrics & Alerts — Latency histograms, queue depth tracking, and configurable alert thresholds.
- Graceful Shutdown — Drain pending commands before stopping.
Architecture
QueueManager
├── EventEmitter ← broadcast pub/sub; subscribe() returns EventStream (Stream)
├── CommandQueue ← scheduler (10ms poll loop)
│ ├── Lanes ← HashMap<LaneId, Lane>
│ │ └── Lane ← priority queue + concurrency semaphore
│ │ ├── Pending ← VecDeque (FIFO within priority)
│ │ └── Config ← timeout, retry, rate limit, boost, pressure threshold
│ ├── DeadLetterQueue ← failed commands
│ └── Storage ← optional persistence
├── Metrics ← optional observability
└── Alerts ← optional monitoringBuilt-in Lanes
Prop
Type
Lower priority number = higher priority. The scheduler always picks commands from the highest-priority lane with pending work.
Supported Languages
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Type
Performance
Benchmarked on Apple Silicon (M-series), release build:
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Type
Test Coverage
246 tests (--all-features). Key modules at 98–100% line coverage.